✨ About The Role
- The internship will involve collaborating with the Advanced Projects Group to propose a project that aligns with personal interests and contributes to ongoing technical challenges.
- Interns will be responsible for developing professionally written, documented, and regression-tested code in languages such as SystemVerilog, Python, or C/C++.
- The role requires identifying and managing milestones, setting actionable goals, and providing weekly status reports on project progress.
- Interns must maintain strict confidentiality regarding the technical details of CesiumAstro's intellectual property.
- A final presentation to CesiumAstro's senior technical and corporate leadership teams will be expected at the conclusion of the internship.
âš¡ Requirements
- The ideal candidate is currently enrolled in a Bachelor's, Master's, or PhD program in a relevant field such as Computer Engineering, Computer Science, Electrical Engineering, Aerospace Engineering, or Physics.
- A strong academic record with a GPA of 3.5 or higher is essential for success in this internship.
- Candidates should have research, internship, or academic experience with DSP algorithm implementation or digital logic design on complex, SoC-class FPGAs.
- Proficiency in programming languages such as SystemVerilog, Verilog, VHDL, Python, MATLAB, or Embedded C is highly desirable.
- A foundational understanding of digital design and engineering principles is crucial for tackling the technical challenges presented in this role.