The Cesium hardware team is looking for Summer 2026 interns to develop HDL-level FPGA systems for satellite communication systems. FPGA development interns will work closely with Cesium engineers on FPGA circuits and systems through all phases of the development process. Areas of focus will include design, verification, testing, and deployment at the HDL level. FPGA HDL designs will include high-speed serial interfaces and data streams, digital processing cores, multiple clock domains, and management interfaces. Testing, validation, and verification will also be central tasks for any FPGA design. Assignments will be determined by a mix of project availability and the interests of the successful candidates. Cesium interns regularly present their work to peers, mentors, and Cesium executive leadership throughout the course of the summer. As such, excellent written and verbal communication skills are required.
To apply, please include a cover letter describing your interest in FPGAs and either space systems or communication systems, as well as your status as a US citizen or permanent resident. We are accepting applications for this role through October 10th, 2025.
All CesiumAstro internships are compensated competitively and located onsite at one of our facilities. CesiumAstro is an Equal Opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, disability, protected Veteran Status, or any other characteristic protected by applicable federal, state, or local law.